1. Field of the Invention
The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for modeling system-level effects of soft errors.
2. Background of the Invention
As technological trends head toward smaller devices and wire dimensions, system design is entering an era of increased chip integration, reduced supply voltages, and higher frequencies. An inescapable consequence of this development is the fact that transient/soft errors will continue to be a serious threat to the general technology of robust computing. Transient errors may occur due to a variety of events, most notable among them being the impact of high energy cosmic particles, alpha particle effects due to the presence of lead in packaging materials, and inductive noise effects (Ldi/dt) on the chip supply voltage resulting from aggressive forms of dynamic power management.
Current soft error rate (SER) projections for Static Random Access Memory (SRAM) cells, latch elements, and logic elements, as technology scales from 65 nm towards 45 nm and beyond, indicate that the SER per bit for SRAM cells appears to be leveling off. However, it must be noted that the bit count per chip is increasing exponentially, per Moore's Law. Latch SER is catching up with SRAM per-bit rates with a steeper slope of increase. Logic SER is projected to increase at a much faster pace, although the absolute numbers are significantly smaller than SRAM or latch numbers at the present time. For Silicon On Insulator (SOI) technology, going forward from 65 nm to 45 nm technology, the latch SER per bit is predicted to increase 2× to 5× fold, and latches per chip are of course expected to increase with integration density. Again, storage cell SER will still dominate and latch errors will also be of increasing relevance at 45 nm technologies and beyond.